1. Field of the Invention:
This invention relates to a charge coupled device (hereinafter, referred to a CCD) having a parallel-serial converting portion, and more particularly to a charge coupled device such as an area image sensor having a plurality of vertical CCD shift-register and a horizontal CCD shift-register receiving charges from the vertical CCD shift-registers for parallel-serial conversion.
2. Background of the Invention:
A CCD area image sensor is formed of a plurality of photo-detector elements arranged in rows and columns, a plurality of vertical CCD registers each disposed in parallel with each column of the photo-detector elements to transfer charges accumulated in the photo-detector elements and a horizontal CCD registers receiving charges from the vertical CCD registers for parallel-serial conversion of charge information. The photo-detectors accumulate charges in response to irradiation of light information. The accumulated charges are simultaneously transferred to the vertical CCD shift-registers to further transfer to the horizontal CCD shift-register. The horizontal CCD shift-register produces the charge information arranged in series which is obtained in a voltage form at a charge-voltage converter provided at an edge of the horizontal CCD shift-register.
The vertical and horizontal CCD shift-registers are driven by two-or four-phase clock pulses. Especially, the horizontal CCD shift-register receives the charges at portions under transfer gate electrodes supplied with the same phase clock from the vertical shift-register. In a non-interlace scanning of the photo-detector array, since the clock pulse applied to the final stage transfer gate electrodes of the vertical CCD shift-registers which are closest to the horizontal CCD shift-register are held at a grounding potential or the lowest potential during the charge-transfer operation of the horizontal CCD shift-register, the charges can be transferred through the horizontal CCD shift-register without going back to the vertical CCD shift-registers. However, in an interlace scanning, the clock pulse applied to the final stage transfer gate electrode changes its phase at every scanning fields. Accordingly, there are scanning fields in which the clock pulse applied to the final stage transfer gate electrode is held at a high potential during the charge transfer operation of the horizontal CCD shift-register. In such case, charges in the horizontal CCD shift-register erroneously go back to the vertical CCD shift-registers.
In order to prevent charges in the horizontal CCD shift-register from going back to the vertical CCD shift-register, the CCD area image sensor in the prior art has a particular final stage electrode in the respective vertical CCD shift-registers. The particular final stage electrode is formed at a position closest to the horizontal CCD shift-register and supplied with a particular pulse. The particular pulse has a high level to allow charges to be transferred from the vertical CCD shift-registers to the horizontal CCD shift-register through the particular final stages. This prior art was proposed in a U.S. Pat. No. 3,971,003 granted to Walter F. Kosonocky.
The proposed measurement has some drawbacks. First is a requirement of a generator of the particular pulse. The CCD area image sensor itself requires many pulses for driving the vertical and horizontal CCD shift-registers, for transferring charges from the photo-detector elements to the vertical CCD shift-registers and for driving other circuit portions such as charge-voltage converter. The increment of necessary pulses makes the pulse generator very complexed. Moreover, if the particular pulse has even a small asynchronism with the operation of the horizontal CCD shift-register, the charges in the horizontal CCD shift-register go back to the vertical CCD shift-register. Therefore, the pulse width of the low level signal in the particular pulse should be designed to be wider than an operating period of the horizontal CCD shift-register for allowing the above-mentioned small asynchronism. This allowance of the pulse width in the particular pulse makes the improvement of high speed operation difficult.
Another measurement in the prior art is application of a particular D.C. potential to the final stage transfer gate electrode instead of the particular pulse. The particular D.C. potential is a half potential of the potential difference between high and low levels of the clock pulses applied to the vertical CCD shift-register. This measurement is somewhat effective in the image sensor using buried channel type CCD shift-registers. The buried channel type CCD keeps some potential well when the clock pulse has a grounding potential. The charges to be stored in a potential difference between the particular D.C. potential and the potential well at the grounding level of clock pulse are a maximum value of charges transferable in the horizontal CCD shift-register. This transferable charge value is easily affected from changes in the particular D.C. potential and impurity concentration of the buried channel type CCD and is impossible to be made large. Furthermore, if the horizontal CCD shift-register is driven in a sharp clock pulse, charges in the horizontal CCD shift-register go back to the vertical CCD shift-registers prior to charge-transfer along the horizontal CCD shift-register. This sharp clock easily appears in normal clock pulse as an undershoot which is caused by capacitive couplings between transfer gate electrodes, resulting in a limit in high speed operation.